Integrated circuits (i.e., chips) typically receive at least one supply voltage from an external power source. When the voltage is first applied to a chip, the chip undergoes "power-up", as the voltage on the chip's supply buses stabilizes at the supply voltage level. The duration of power-up generally depends on the capacitive loading of the supply buses and the slew rate of the supply voltages.
In addition, some chips include an "on-chip" voltage generator to generate a supply voltage that is not provided externally, but is used internally by the integrated circuit. For example, in some integrated circuit memory devices, a boosted voltage supply is used in boosted word line designs or to provide rail-to-rail output signals with N-channel pull-up devices in output circuits. However, the boosted voltage must be tightly regulated to save power and prevent damage to other circuit devices.
FIG. 1 shows a regulator system 10 for an on-chip-generated supply voltage. System 10 includes a voltage divider 11, a voltage reference 13, a threshold detector 15 and a buffer 16. Voltage divider 11 is connected to receive the boosted supply voltage V.sub.H and output to threshold detector 15 a voltage V.sub.SH having a value that is a scaled version of (i.e., proportional) the value of the boosted supply voltage V.sub.H. Threshold detector 15 then compares scaled voltage V.sub.SH from voltage divider 11 to a reference voltage V.sub.REF from voltage reference 13. Voltage divider 11 and voltage reference 13 are designed so that, ideally, their output voltages V.sub.SH and V.sub.REF have the same value when the value of boosted supply voltage V.sub.H is at the desired level. Threshold detector 15 compares the levels of voltages V.sub.SH and V.sub.REF and generates an output signal with a logic level indicative of whether the value of scaled voltage V.sub.SH is greater than or less than reference voltage V.sub.REF. The output signal of threshold detector 15 is propagated to buffer 16, which outputs a boost control signal BC. Boost control signal BC is propagated to a charge pump (not shown) to control the activation and deactivation of the charge pump. In particular, the charge pump is configured to be activated when the logic level of signal BC indicates that the value of scaled voltage V.sub.SH is lower than reference voltage V.sub.REF and to be de-activated when signal BC indicates that the value of scaled voltage V.sub.SH is equal to or greater than reference voltage V.sub.REF. Thus, during power-up the charge pump is disabled until voltage V.sub.REF reaches its desired level.
One problem with conventional system 10 is that voltage reference 13 generally does not accurately generate voltage V.sub.REF unless the supply voltage VDD is stable. Moreover, the accuracy of voltage reference 13 is generally not predictable during power-up. As a result, during power-up, threshold detector 15 may generate signal BC so as to limit on-chip-generated supply voltage V.sub.H below its desired level (i.e., underpumping). This underpumping may damage circuits that use on-chip-generated supply voltage V.sub.H. For example, underpumping may result in latch-up of P-channel pass transistors in the charge pump (not shown). More specifically, underpumping may cause latch-up between voltages V.sub.H and VDD by forward biasing the source/drain regions with respect to the N-well of the P-channel pass transistors.
Waveform 21 in FIG. 2 represents the level of supply voltage VDD during power up. Ideally, voltage V.sub.H will ramp up so as to reach the desired level at about the same time as supply voltage VDD reaches its desired level, as indicated by waveform 22. However, the prior approach disables the charge pump (not shown) until supply voltage V.sub.REF reaches its desired level. Waveform 24 represents the level of supply voltage V.sub.REF. When the level of supply voltage V.sub.REF reaches the desired level, the charge pump is enabled, causing the level of boosted voltage V.sub.H to increase. This delay in enabling the charge pump causes boosted voltage V.sub.H to reach its desired level later in time, as indicated by waveform 23. This delay undesirably increases the chip's power-up time and probability of latch-up. Accordingly, there is a need for a regulator system that more accurately regulates an on-chip-generated supply voltage during power-up.